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Verilog Programming Language

Verilog is a Hardware Description Language (HDL). It is a language used for describing a digital system such as a network switch, a microprocessor, a memory, or a flip-flop. We can describe any digital hardware by using HDL at any level. Designs described in HDL are independent of technology, very easy for designing and debugging, and are normally more useful than schematics, particularly for large circuits. Verilog was developed to simplify the process and make the HDL more robust and flexible. Today, Verilog is the most popular HDL used and practiced throughout the semiconductor industry.


// This is my first Verilog Program
// Design Name : hello_world
// File Name : hello_world.v
// Function : This program will print 'hello world'
// Coder    : Deepak

module hello_world ;
initial begin  
   $display ("Hello World by Deepak");
   #10  $finish;
 endmodule // End of Module hello_world


Verilog was created by Prabhu Goel, Phil Moorby, Chi-Lai Huang, and Douglas Warmke between late 1983 and early 1984. Chi-Lai Huang had earlier worked on a hardware description LALSD, a language developed by Professor S.Y.H. Su, for his PhD work The rights holder for this process, at the time proprietary, was "Automated Integrated Design Systems" (later renamed to Gateway Design Automation in 1985). Gateway Design Automation was purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de facto standard (of Verilog logic simulators) for the next decade. Originally, Verilog was only intended to describe and allow simulation; the automated synthesis of subsets of the language to physically realizable structures (gates etc.) was developed after the language had achieved widespread usage. Verilog is a portmanteau of the words "verification" and "logic


  • Compact language.

    • Small code footprint.

    • Familiar language conventions similar to C.

    • Mixing and matching signals is very easy.

  • Reduction operators.

    • Perform logical tests on an entire array of bits with a single operator.

  • Low-level descriptions closer to actual hardware.

    • Instantiate gates directly.

    • Explicitly declare wires and registers directly.

  • Compiler directives.


  • Weakly-typed language.

    • Code is more error prone due to accidental combination of differing signal types.

    • Possible to create signal with a typo.

  • No sensitivity lists.

    • Less of a chance of design synthesis and simulation problems arising from coding.

  • No support of custom types.

    • State machine coding is more difficult because states must be numeric values with a static bit widths (techniques exist to ease this problem).

  • Confusing signal declarations.

    • Signal declarations are not always required.

    • The difference between a wire and reg is not always obvious for beginners, and a reg can sometimes be a wire.

  • Confusing language conventions for beginners.

    • The difference between blocking and non-blocking statements is sometimes difficult to grasp for beginning FPGA programmers

  • Reduced support for asynchronous signals.

    • Using asynchronous signals slows down simulation software.

    • Language constructs don’t support natural usage of asynchronous signals.

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